View MAX704212_4678034.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the max7042 fully integrated, low-power, cmos superheterodyne rf receiver is designed to receive frequency-shift-keyed (fsk) data at rates up to 66kbps nonreturn-to-zero (nrz) (33kbps manchester). the max7042 requires only a few external components to realize a complete wireless rf receiver at 308, 315, 418, and 433.92mhz. the max7042 includes all the active components required in a superheterodyne receiver including a low- noise amplifier (lna), an image-rejection (ir) mixer, a fully integrated phase-locked loop (pll), local oscillator (lo), 10.7mhz if limiting amplifier with received-signal- strength indicator (rssi), low-noise fm demodulator, and a 3v regulator. differential peak-detecting data demodulators are included for baseband data recovery. the max7042 is available in a 32-pin tqfn and is specified over the automotive -40c to +125c tem- perature range. applications remote keyless entry tire-pressure monitoring home and office lighting control remote sensing smoke alarms home automation local telemetry systems security systems features +2.4v to +3.6v or +4.5v to +5.5v single-supply operation four user-selectable carrier frequencies 308, 315, 418, and 433.92mhz -110dbm rf input sensitivity at 315mhz -109dbm rf input sensitivity at 433.92mhz fast startup (< 250 s) small 32-pin tqfn package low operating supply current 6.2ma continuous 20na power-down integrated pll, vco, and loop filter 45db integrated image rejection selectable if bw with external filter positive and negative peak detectors rssi output max7042 308mhz/315mhz/418mhz/433.92mhz low-power, fsk superheterodyne receiver ________________________________________________________________ maxim integrated products 1 24 23 22 21 20 19 18 1234567 10 11 12 13 14 15 16 31 30 29 28 27 26 25 max7042 tqfn top view en n.c. fsel1 fsel2 hvin data lnasel 32 ep n.c. n.c. n.c. n.c. rssi xtal2 xtal1 avdd lnain dvdd dgnd df op+ ds+ ds- pdmax 17 pdmin ifin+ ifin- agnd mixout mixin- mixin+ lnaout 9 lnasrc 8 + pin configuration ordering information 19-3704; rev 2; 1/12 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. evaluation kit available part temp range pin-package max7042atj+ -40c to +125c 32 tqfn-ep* typical application circuit appears at end of data sheet.
max7042 308mhz/315mhz/418mhz/433.92mhz low-power, fsk superheterodyne receiver 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics ( typical application circuit , 50 ? system impedance, v avdd = v dvdd = v hvin = +2.4v to +3.6v, f rf = 308, 315, 418, and 433.92mhz; t a = -40c to +125c, unless otherwise noted. typical values are at v avdd = v dvdd = v hvin = +3.0v, f rf = 433.92mhz, p rfin -80dbm, t a = +25c, unless otherwise noted.) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. hvin to agnd or dgnd .......................................-0.3v to +6.0v avdd, dvdd to agnd or dgnd..........................-0.3v to +4.0v fsel1, fsel2, lnasel, en, data...............................(dgnd - 0.3v) to (hvin + 0.3v) all other pins............................(agnd - 0.3v) to (avdd + 0.3v) continuous power dissipation (t a = +70c) 32-pin tqfn (derate 34.5mw/c above +70c)..........2759mw operating temperature range .........................-40c to +125c storage temperature range .............................-65c to +150c maximum rf input power ................................................+0dbm lead temperature (soldering, 10s) .................................+300c soldering temperature (reflow) .......................................+260c parameter symbol conditions min typ max units supply voltage (3v) v dd hvin, avdd, and dvdd connected to power supply 2.4 3.0 3.6 v supply voltage (5v) hvin hvin connected to power supply, avdd and dvdd unconnected from hvin, but connected together 4.5 5.0 5.5 v operating, 1x i lna 6.2 315m h z ( 3v ) operating, 2x i lna 6.8 operating, 1x i lna 6.4 315m h z ( 5v ) operating, 2x i lna 7.0 operating, 1x i lna 6.4 8.7 434m h z ( 3v ) operating, 2x i lna 7.0 8.6 operating, 1x i lna 6.6 8.4 supply current i dd 434m h z ( 5v ) operating, 2x i lna 7.2 9.2 ma t a = +25c 0.02 t a = +85c 0.1 shutdown current (3v) i shdn all digital inputs low t a = +125c 0.85 6 a t a = +25c 0.6 t a = +85c 1.4 shutdown current (5v) i shdn all digital inputs low t a = +125c 4 7 a startup time t on time from en = high to final signal detection; does not include baseband filter or data- slicer reference settling 250 s digital i/o input high threshold v ih 0.9 x v hvin v input low threshold v il 0.1 x v hvin v
max7042 308mhz/315mhz/418mhz/433.92mhz low-power, fsk superheterodyne receiver _______________________________________________________________________________________ 3 dc electrical characteristics (continued) ( typical application circuit , 50 ? system impedance, v avdd = v dvdd = v hvin = +2.4v to +3.6v, f rf = 308, 315, 418, and 433.92mhz; t a = -40c to +125c, unless otherwise noted. typical values are at v avdd = v dvdd = v hvin = +3.0v, f rf = 433.92mhz, p rfin -80dbm, t a = +25c, unless otherwise noted.) parameter symbol conditions min typ max units v hvin = +3.6v 8 15 input high pulldown current i ih v hvin = +5.5v 20 40 a v hvin = +3.6v < 1 1 input low-leakage current i il v hvin = +5.5v < 1 1 a output high voltage v oh i source = 500a v hvin - 0.4 v output low voltage v ol i sink = 500a 0.4 v voltage regulator output voltage v reg 2.5 3.0 3.5 v ac electrical characteristics ( typical application circuit , 50 ? system impedance, v avdd = v dvdd = v hvin = +2.4v to +3.6v, f rf = 308, 315, 418, and 433.92mhz; t a = -40c to +125c, unless otherwise noted. typical values are at v avdd = v dvdd = v hvin = +3.0v, f rf = 433.92mhz, p rfin -80dbm, t a = +25c, unless otherwise noted.) parameter symbol conditions min typ max units maximum input level 0 dbm operating, 1x i lna -107 315mhz setting operating, 2x i lna -110 operating, 1x i lna -106 sensitivity (note 1) 434mhz setting operating, 2x i lna -109 dbm receiver image rejection 45 db lna/mixer 2x i lna 315mhz 0.94 - j3.2 input impedance (note 2) z in_lna normalized to 50 ? 2x i lna 433.92mhz 0.94 - j2.1 1x i lna 315mhz -47 1db input compression point p 1db 2x i lna 315mhz -52 dbm 1x i lna 315mhz -37 input-referred 3rd-order intercept point iip3 2x i lna 315mhz -42 dbm lo signal feedthrough to antenna -80 dbm mixer output impedance zout mix 330 ? 1x i lna 315mhz 52 2x i lna 315mhz 57 1x i lna 433.92mhz 47 voltage conversion gain 330 ? if filter load (note 3) 2x i lna 433.92mhz 52 db if limiting amplifier input impedance z in_if 330 ? -3db bandwidth 10 mhz
max7042 308mhz/315mhz/418mhz/433.92mhz low-power, fsk superheterodyne receiver 4 _______________________________________________________________________________________ note 1: 0.2% ber, 4kbps, manchester coded, 280khz if bw, 50khz frequency deviation. note 2: input impedance is measured at the lnain pin. note that the impedance at 315mhz includes the 3.9nh inductive degener- ation from the lna source to ground. the impedance at 433.92mhz includes a 0nh inductive degeneration connected from the lna source to ground. the equivalent input circuit is 47 ? in series with 3.2pf at 315mhz and 47 ? in series with 3.5pf at 433.92mhz. note 3: the voltage conversion gain is measured with the lna input matching inductor, the degeneration inductor, and the lna/mixer resonator in place, and does not include the if filter insertion loss. ac electrical characteristics (continued) ( typical application circuit , 50 ? system impedance, v avdd = v dvdd = v hvin = +2.4v to +3.6v, f rf = 308, 315, 418, and 433.92mhz; t a = -40c to +125c, unless otherwise noted. typical values are at v avdd = v dvdd = v hvin = +3.0v, f rf = 433.92mhz, p rfin -80dbm, t a = +25c, unless otherwise noted.) parameter symbol conditions min typ max units operating frequency f if 10.7 mhz rssi slope 10 16 21 mv/db fsk demodulator conversion gain 1.1 2.1 3.0 mv/khz analog baseband m axi m um p eak- d etector band w i d th 50 khz maximum data-filter bandwidth bw df 50 khz maximum data-slicer bandwidth bw ds 100 khz manchester coded 33 maximum data rate nrz 66 khz crystal oscillator crystal frequency f xtal (f rf - 10.7) / 32 mhz crystal load capacitance 4.5 pf 5.4 5.8 5.6 6.4 6.2 6.0 7.0 6.8 6.6 7.2 2.4 3.0 2.7 3.3 3.6 supply current vs. supply voltage (1x i lna ) max7042 toc01 supply voltage (v) supply current (ma) -40 c +125 c +85 c +25 c 6.0 6.4 6.2 7.0 6.8 6.6 7.6 7.8 7.4 7.2 8.0 2.4 3.0 2.7 3.3 3.6 supply current vs. supply voltage (2x i lna ) max7042 toc02 supply voltage (v) supply current (ma) -40 c +25 c +125 c +85 c 5.6 6.0 5.8 6.4 6.2 6.8 6.6 7.0 300 350 375 325 400 425 450 supply current vs. rf frequency (1x i lna ) max7042 toc03 rf frequency (mhz) supply current (ma) +125 c +85 c +25 c -40 c typical operating characteristics ( typical application circuit , v dd = 3.0v, f rf = 433.92mhz, if bw = 280khz, data rate = 4kbps manchester encoded, frequency deviation = 50khz, ber = 0.2%, t a = +25c, unless otherwise noted.)
max7042 308mhz/315mhz/418mhz/433.92mhz low-power, fsk superheterodyne receiver _______________________________________________________________________________________ 5 6.1 6.5 6.3 6.9 6.7 7.3 7.1 7.5 300 350 375 325 400 425 450 supply current vs. rf frequency (2x i lna ) max7042 toc04 rf frequency (mhz) supply current (ma) +125 c +85 c +25 c -40 c deep-sleep current vs. temperature max7042 toc05 temperature ( c) deep-sleep current (na) 110 85 60 35 10 -15 200 400 600 800 1000 0 -40 v dd = +3.6v v dd = +3.0v v dd = +2.4v bit-error rate vs. average input power (1x i lna ) max7042 toc06 average input power (dbm) bit-error rate (%) -106 -108 -110 -112 0.1 1 10 100 0.01 -114 -104 f rf = 433.92mhz 0.2% ber f rf = 315mhz bit-error rate vs. average input power (2x i lna ) max7042 toc07 average input power (dbm) bit-error rate (%) -109 -113 -111 -115 0.1 1 10 100 0.01 -117 -107 f rf = 433.92mhz 0.2% ber f rf = 315mhz sensitivity (dbm) -108 -107 -106 -105 -104 -103 -109 sensitivity vs. temperature (1x i lna ) max7042 toc08 temperature ( c) 110 85 60 35 10 -15 -40 f rf = 433.92mhz f rf = 315mhz sensitivity (dbm) -111 -110 -109 -108 -107 -106 -112 sensitivity vs. temperature (2x i lna ) max7042 toc09 temperature ( c) 110 85 60 35 10 -15 -40 f rf = 433.92mhz f rf = 315mhz sensitivity vs. frequency deviation max7042 toc10 frequency deviation (khz) sensitivity (dbm) 10 -110 -108 -106 -104 -102 -100 -112 1 100 frequency deviation is measured from 0 to peak 0 0.6 0.3 1.2 0.9 1.5 1.8 -3 -1 -2 1 0 2 3 -90 -50 -30 -70 -10 10 rssi and delta vs. if input power max7042 toc11 if input power (dbm) rssi (v) delta (%) rssi delta 0 0.8 0.4 1.6 1.2 2.0 10.3 10.5 10.6 10.4 10.8 10.7 10.9 11.0 fsk demodulator output vs. if frequency max7042 toc12 if frequency (mhz) fsk demodulation output (v) typical operating characteristics (continued) ( typical application circuit , v dd = 3.0v, f rf = 433.92mhz, if bw = 280khz, data rate = 4kbps manchester encoded, frequency deviation = 50khz, ber = 0.2%, t a = +25c, unless otherwise noted.)
max7042 308mhz/315mhz/418mhz/433.92mhz low-power, fsk superheterodyne receiver 6 _______________________________________________________________________________________ system gain vs. if frequency (1x i lna ) max7042 toc13 if frequency (mhz) system gain (db) 25 20 15 10 5 0 10 20 30 40 50 -10 030 lower sideband upper sideband from rfin to mixout f rf = 433.92mhz 45db image rejection system gain vs. if frequency (2x i lna ) max7042 toc14 if frequency (mhz) system gain (db) 25 20 15 10 5 0 10 20 30 40 50 60 -10 030 lower sideband upper sideband from rfin to mixout f rf = 433.92mhz 45db image rejection image rejection (db) 10 20 30 40 50 60 0 image rejection vs. temperature (1x i lna ) max7042 toc15 temperature ( c) 110 85 60 35 10 -15 -40 f rf = 433.92mhz f rf = 315mhz image rejection (db) 10 20 30 40 50 60 0 image rejection vs. temperature (2x i lna ) max7042 toc16 temperature ( c) 110 85 60 35 10 -15 -40 f rf = 433.92mhz f rf = 315mhz 1 10 100 normalized if gain vs. if frequency max7042 toc17 if frequency (mhz) normalized if gain (db) -18 -9 -6 -15 -12 -3 0 s11 vs. rf frequency max7042 toc18 rf frequency (mhz) s11 (db) 850 700 550 400 250 -12 -8 -4 0 -16 100 1000 433.92mhz typical operating characteristics (continued) ( typical application circuit , v dd = 3.0v, f rf = 433.92mhz, if bw = 280khz, data rate = 4kbps manchester encoded, frequency deviation = 50khz, ber = 0.2%, t a = +25c, unless otherwise noted.)
max7042 308mhz/315mhz/418mhz/433.92mhz low-power, fsk superheterodyne receiver _______________________________________________________________________________________ 7 s11 smith plot of r fin max7042 toc19 433.92mhz input impedance vs. inductive degeneration max7042 toc20 inductive degeneration (nh) real impedance ( ? ) 10 30 40 50 60 70 20 imaginary impedance ( ? ) -190 -180 -170 -160 -150 -200 1 100 f rf = 315mhz imaginary impedance real impedance input impedance vs. inductive degeneration max7042 toc21 inductive degeneration (nh) real impedance ( ? ) 10 30 40 50 60 70 80 90 20 imaginary impedance ( ? ) -130 -120 -110 -100 -140 1 100 f rf = 433.92mhz imaginary impedance real impedance -70 -130 100 10k 1k 100k 1m 10m phase noise vs. offset frequency -120 -110 -90 -100 -80 max7042 toc22 offset frequency (hz) phase noise (dbc/hz) f rf = 315mhz f rf = 433.92mhz typical operating characteristics (continued) ( typical application circuit , v dd = 3.0v, f rf = 433.92mhz, if bw = 280khz, data rate = 4kbps manchester encoded, frequency deviation = 50khz, ber = 0.2%, t a = +25c, unless otherwise noted.)
max7042 308mhz/315mhz/418mhz/433.92mhz low-power, fsk superheterodyne receiver 8 _______________________________________________________________________________________ pin description pin name function 1, 2 n.c. no connection. internally pulled down. 3, 25, 32 n.c. no connection. not internally connected. 4 rssi buffered received-signal-strength-indicator output 5 xtal2 crystal input 2. xtal2 can be driven from an ac-coupled external reference. 6 xtal1 crystal input 1. bypass to gnd if xtal2 is driven by an ac-coupled external reference. 7 avdd analog power-supply voltage. avdd is connected to an on-chip +3.0v regulator in +5v operation. bypass avdd to gnd with 0.1f and 220pf capacitors placed as close to the pin as possible. 8 lnain low-noise amplifier input. must be ac-coupled. 9 lnasrc low-noise amplifier source for external inductive degeneration. connect an inductor to gnd to set the lna input impedance. 10 lnaout low-noise amplifier output. connect to v avdd through a parallel lc tank filter. ac-couple to mixin+. 11 mixin+ noninverting mixer input. must be ac-coupled to the lna output. 12 mixin- inverting mixer input. bypass to v avdd or agnd with a capacitor. 13 mixout 330 ? mixer output. connect to the input of the 10.7mhz if filter. 14 agnd analog ground 15 ifin- inverting 330 ? if limiter amplifier input. bypass to agnd with a capacitor. 16 ifin+ noninverting 330 ? if limiter amplifier input. connect to the output of the 10.7mhz if filter. 17 pdmin minimum-level peak detector for demodulator output 18 pdmax maximum-level peak detector for demodulator output 19 ds- inverting data-slicer input 20 ds+ noninverting data-slicer input 21 op+ noninverting op-amp input for the sallen-key data filter 22 df data-filter feedback node. input for the feedback of the sallen-key data filter. 23 dgnd digital ground 24 dvdd digital power-supply voltage. bypass to dgnd with 0.01f and 220pf capacitors placed as close to the pin as possible. 26 en enable. internally pulled down. drive high for normal operation. drive low or leave unconnected to put the device into shutdown mode. 27 fsel1 frequency-select pin 1 (see table 1). internally pulled down. connect to en for logic-high operation. 28 fsel2 frequency-select pin 2 (see table 1). internally pulled down. connect to en for logic-high operation. 29 hvin high-voltage supply input. for +3v operation, connect hvin to avdd and dvdd. for +5v operation, connect only hvin to +5v. bypass hvin to agnd with 0.01f and 220pf capacitors placed as close to the pin as possible. 30 data receiver data output 31 lnasel lna bias current select pin. internally pulled down. set lnasel to logic-low for low lna current and set lnasel to logic-high for high lna current. connect to en for logic-high operation. ep gnd exposed pad. connect to ground.
max7042 308mhz/315mhz/418mhz/433.92mhz low-power, fsk superheterodyne receiver _______________________________________________________________________________________ 9 10 30 8 9 14 6 5 26 24 23 29 7 *must be connected to agnd. 19 18 17 20 21 22 11 12 13 15 16 4 rssi lnasel fsel2 fsel1 27 28 31 lnaout mixin+ mixin- 0? 90? ifin- mixout ifin+ rssi if limiting amps lnasrc lnain fsk demodulator fsk image rejection 3.0v r df1 100k ? r df2 100k ? df op+ ds+ pdmax ds- data pdmin divide- by-32 vco loop filter phase detector crystal oscillator xtal1 xtal2 fsk data filter en agnd hvin 3.0v reg dgnd avdd dvdd exposed pad* max7042 lna functional diagram
max7042 308mhz/315mhz/418mhz/433.92mhz low-power, fsk superheterodyne receiver 10 ______________________________________________________________________________________ detailed description the max7042 cmos superheterodyne receiver and a few external components provide a complete fsk receive chain from the antenna to the digital output data. fsk uses the difference in frequency of the carri- er to represent a logic 0 and logic 1. depending on sig- nal power and component selection, data rates as high as 66kbps nrz can be achieved. frequency selection the max7042 can be tuned to one of four frequencies using the 2 frequency-select bits fsel1 and fsel2: 308, 315, 418, and 433.92mhz, as shown in table 1. the lo frequencies are 32 times the crystal reference frequencies of 9.29063, 9.50939, 12.72813, and 13.22563mhz. the selected crystal frequency is used to calibrate the fsk detector pll so that it operates at the middle of the 10.7mhz if. low-noise amplifier (lna) the lna is a cascode amplifier with off-chip inductive degeneration. the gain and the noise figure are depen- dent on both the antenna matching network at the lna input and the lc tank network between the lna output and the mixer input. the max7042 allows for user programmability of the lna bias current. input lnasel programs 1x to 2x bias currents in increments of 0.6ma from 0.6ma to 1.2ma. setting lnasel to logic-low programs the lna to consume 1x bias current and setting lnasel to logic-high programs the lna to consume 2x bias cur- rent. larger bias currents yield better sensitivity and gain at the expense of current drain. the off-chip inductive degeneration is achieved by connecting an inductor from lnasrc to agnd. this inductor sets the real part of the input impedance at lnain, allowing for a more flexible match to a low-input impedance such as printed circuit board (pcb) trace antenna. a nominal value of this inductor for a 50 ? input impedance is 3.9nh at 315mhz and 0nh (short) at 433.92mhz, but is affected by the pcb trace. see the typical operating characteristics for the relationship between the inductance and input impedance. the lc tank filter connected to lnaout consists of l2 and c9 (see the typical application circuit ). select l2 and c9 to resonate at the desired rf input frequency. the resonant frequency is given by: where l total = l2 + l parasitics and c total = c9 + c parasitics . l parasitics and c parasitics include inductance and capacitance of the pcb traces, package pins, mixer input impedance, lna output impedance, etc. these parasitics at high frequencies cannot be ignored, and can have a dramatic effect on the tank filter center fre- quency. lab experimentation is required to optimize the center frequency of the tank. the parasitic capacitance is generally 5pf to 7pf. there are two ways to verify experimentally that the res- onant frequency of the tank is centered at the desired rf frequency: 1) drive the crystal oscillator externally and sweep both the rf frequency and the lo frequency (fxtal x 32) to keep the if at 10.7mhz while monitoring the rssi voltage (pin 4). there is a peak in the rssi voltage at resonance. the external source must be ac-coupled into xtal1 and the xtal2 pin must have an ac bypass to ground. the recommended drive power is -10dbm. 2) use a network analyzer to measure the resonance. the port 1 power from the network analyzer is input to the receiver, and this power must be -30dbm or less. a coaxial stub with the center conductor exposed (commonly called an rf sniffer is used to monitor the tank power and serves as the port 2 input to the network analyzer. the sniffer should be placed in close proximity to, but not actually touch- ing, the tank inductor. f lxc total total = 1 2 table 1. frequency selection table fsel2 fsel1 frequency (mhz) 0 0 308 0 1 315 1 0 418 1 1 433.92
max7042 308mhz/315mhz/418mhz/433.92mhz low-power, fsk superheterodyne receiver ______________________________________________________________________________________ 11 mixer a unique feature of the max7042 is the integrated image rejection of the mixer. this device is designed to elimi- nate the need for a costly front-end saw filter in many applications. the advantages of not using a saw filter are increased sensitivity, simplified antenna matching, less board space, and lower cost. the mixer cell is a pair of double-balanced mixers that perform an iq downconversion of the rf input to the 10.7mhz intermediate frequency (if) with low-side injection (i.e., f lo = f rf - f if ). the image-rejection circuit then combines these signals to achieve a typical image rejection of approximately 45db. low-side injection is required as high-side injection is not possible due to the on-chip image rejection. the if output is driven by a source follower, biased to create a driving imped- ance of 330 ? to interface with an off-chip 330 ? ceram- ic if filter. note that mixin+ and mixin- are functionally identical. phase-locked loop (pll) the pll block contains a phase detector, charge pump/integrated loop filter, voltage-controlled oscillator (vco), asynchronous 32x frequency divider, and crys- tal oscillator. this pll does not require any external components. the relationship between the rf, if, and crystal reference frequencies is given by: for additional information on proper crystal selection, see the crystal oscillator and frequency tolerance sections. intermediate frequency (if) the if section presents a differential 330 ? load to pro- vide matching for the off-chip ceramic filter. the inter- nal six ac-coupled limiting amplifiers produce an overall gain of approximately 65db. the limiting ampli- fiers have a bandpass-filter-type response centered near the 10.7mhz if frequency with a 3db bandwidth of approximately 10mhz. the limiter output is fed into a pll to demodulate the if, producing a baseband volt- age with a demodulation slope of 2.1mv/khz. the rssi circuit produces a dc output proportional to the log of the if signal level with a slope of approximately 16mv/db. fsk demodulator the fsk demodulator uses an integrated 10.7mhz pll that tracks the input rf modulation and determines the difference between frequencies as logic ones and zeros. the pll is illustrated in figure 1. the input to the pll comes from the output of the if limiting amplifiers. the pll control voltage responds to changes in the fre- quency of the input signal with a nominal gain of 2.1mv/khz. for example, an fsk peak-to-peak devia- tion of 50khz generates a 105mv p-p signal on the con- trol line. this control line is then filtered and sliced by the fsk baseband circuitry. the fsk demodulator pll requires calibration to over- come variations in process, voltage, and temperature. the maximum calibration time is 120s, which is includ- ed in the startup time. recalibration is necessary after a significant change in temperature or supply voltage. calibration occurs automatically each time the max7042 is powered up. drive en low and then high to force a recalibration. en must be driven from low to high after the max7042 supply voltage is stable for proper initial fsk calibration. f ff xtal rf if () = ? 32 loop filter phase detector if limiting amps to fsk baseband filter and data slicer 10.7mhz vco 2.1mv/khz charge pump figure 1. fsk demodulator pll block diagram
max7042 308mhz/315mhz/418mhz/433.92mhz low-power, fsk superheterodyne receiver 12 ______________________________________________________________________________________ crystal oscillator the xtal oscillator in the max7042 is used to generate the lo for mixing with the received signal. the xtal oscil- lator frequency sets the received signal frequency as: f receive = (f xtal x 32) + 10.7mhz the received image frequency at: f image = (f xtal x 32) - 10.7mhz is suppressed by the integrated quadrature image- rejection circuitry. the xtal oscillator in the max7042 is designed to pre- sent a capacitance of approximately 3pf between xtal1 and xtal2. in most cases, this corresponds to a 4.5pf load capacitance applied to the external crystal when typical pcb parasitics are added. it is very impor- tant to use a crystal with a load capacitance that is equal to the capacitance of the max7042 crystal oscillator plus pcb parasitics. if a crystal designed to oscillate with a different load capacitance is used, the crystal is pulled away from its intended operating frequency, introducing an error in the reference frequency. crystals designed to operate with higher differential load capacitance always pull the reference frequency higher. in reality, the oscillator pulls every crystal. a crystals nat- ural frequency is really below its specified frequency, but when loaded with the specified load capacitance, the crystal is pulled and oscillates at its specified frequency. this pulling is accounted for in the specification of the load capacitance. additional pulling can be calculated if the electrical parameters of the crystal are known. the frequency pulling is given by: where: f p is the amount the crystal frequency is pulled in ppm. c m is the motional capacitance of the crystal. c case is the case capacitance. c spec is the specified load capacitance. c load is the actual load capacitance. when the crystal is loaded as specified, i.e., c load = c spec , the frequency pulling equals zero. frequency tolerance the frequency tolerance of the crystal, the frequency and bandwidth tolerance of the if filter, and the desired modulation bandwidth of the signal are all interrelated. the combination of these characteristics should be such to ensure that the modulated signal bandwidth stays within the passband of the if filter after downconversion. as is shown below, a 50ppm tolerance crystal in combi- nation with a 280khz bandwidth if filter is sufficient for most fsk-modulated signals. smaller if filter bandwidths can be used if high-tolerance crystals are used for generating both transmitter and max7042 receiver pll references. the modulated spec- trum of the transmitted signal must be downconverted by the max7042 to fall within the passband of the if filter. the crystal tolerances must take into account the initial +25c tolerance, aging, load capacitance tolerances, and temperature drift for both the transmitter and max7042 receiver. to achieve acceptable signal recep- tion, the following equation must hold: 2 x ( ? f tx + ? f rx + ? f if + f dev + 5 x f mod ) < ifbw min where: ? f tx = (transmitter crystal tolerance in ppm) x (carrier frequency in mhz). this includes aging, load capaci- tance, and temperature effects for the crystal tolerance. ? f rx = (max7042 crystal tolerance in ppm) x (carrier frequency in mhz). this includes aging, load capaci- tance, and temperature effects for the crystal tolerance. ? f if = the center frequency tolerance of the selected if filter. this includes temperature drift of the if filter center frequency. f dev = fsk frequency deviation from carrier frequency. f mod = one half of nrz data rate, or the data rate if manchester coding is used. ifbw min = the minimum bandwidth of the selected if filter. as an example, assume 315mhz carrier frequency, 50ppm crystal tolerances for both transmitter and max7042, 30khz if filter center frequency tolerance, 50khz frequency deviation, and 4.8khz manchester data rate: 2 x [(315 x 50) + (315 x 50) + 30000 +50000 + 5 x 4800] = 271khz < ifbw min this operating condition necessitates a 280khz if filter. f c cc cc x p m case load case spec = + ? + ? ? ? ? ? ? 2 11 10 6
max7042 308mhz/315mhz/418mhz/433.92mhz low-power, fsk superheterodyne receiver ______________________________________________________________________________________ 13 data filters the data filter is implemented as a 2nd-order lowpass sallen-key filter. the pole locations are set by the com- bination of two on-chip resistors and two external capacitors. adjusting the value of the external capaci- tors changes the corner frequency to optimize for dif- ferent data rates. the corner frequency in khz should be to approximately the fastest expected data rate in kbps for nrz and twice the fastest expected data rate in kbps for manchester coding from the transmitter. keeping the corner frequency near the data rate rejects any noise at higher frequencies, resulting in an increase in receiver sensitivity. the configuration shown in figure 2 creates a butterworth or bessel response. the butterworth filter offers a very flat amplitude response in the passband and a rolloff rate of 40db/decade for the two-pole filter. the bessel filter has a linear phase response, which works well for filter- ing digital data. to calculate the value of the capacitors, use the following equations along with the coefficients in table 2: where f c is the desired 3db corner frequency. for example, choose a butterworth filter response with a 5khz corner frequency: choosing standard capacitor values changes c f1 to 470pf and c f2 to 220pf. in the typical application circuit , c f1 and c f2 are named c4 and c3, respectively. data slicer the purpose of a data slicer is to take the analog output of a data filter and convert it to a digital signal. this is achieved by using a comparator and comparing the ana- log input to a threshold voltage. the threshold voltage is set by the voltage on the ds- pin, which is connected to the negative input of the data-slicer comparator. the pos- itive input of the data-slicer comparator is connected to the output of the data filter internally. c k khz pf c k khz pf f f 1 2 1 000 1 414 100 3 14 5 450 1 414 4 100 3 14 5 225 . ( . )( )( . )( ) . ( )( )( . )( ) = = ? ? c b ak f c a kf f c f c 1 2 100 4 100 ()()() ()()() = = ? ? table 2. coefficients to calculate c f1 and c f2 filter type a b butterworth (q = 0.707) 1.414 1.000 bessel (q = 0.577) 1.3617 0.618 fsk demod 100k ? ds+ op+ c f2 c f1 df 100k ? max7042 figure 2. sallen-key lowpass data filter
max7042 308mhz/315mhz/418mhz/433.92mhz low-power, fsk superheterodyne receiver 14 ______________________________________________________________________________________ numerous configurations can be used to generate the data-slicer threshold. for example, the circuit in figure 3 shows a simple method using only one resistor and one capacitor. this configuration averages the analog out- put of the filter and sets the threshold to approximately 50% of that amplitude. with this configuration, the threshold automatically adjusts as the analog signal varies, minimizing the possibility for errors in the digital data. the values of r and c affect how fast the thresh- old tracks the analog amplitude. be sure to keep the corner frequency of the rc circuit much lower than the lowest expected data rate. with this configuration, a long string of zeros or ones can cause the threshold to drift. this configuration works best if a coding scheme, such as manchester coding, which has an equal number of zeros and ones, is used. figure 4 shows a configuration that uses the positive and negative peak detectors to generate the threshold. this configuration sets the threshold to the midpoint between a high output and a low output of the data filter. peak detectors the maximum peak detector (pdmax) and minimum peak detector (pdmin) outputs, in conjunction with a resistor and capacitor connected to gnd, create dc output voltages proportional to the high- and low-peak values of the data signal. the resistor provides a path for the capacitor to discharge, allowing the peak detec- tor to dynamically follow peak changes of the data-filter output voltage. the positive and negative peak detectors can be used together to form a data-slicer threshold voltage at a midvalue between the most positive and most negative voltage levels of the data stream (see the data slicers section and figure 4). set the rc time constant of the peak-detector combining network to at least 5 times the data period. the max7042 peak detectors track the baseband filter output voltage until all internal circuits are stable follow- ing an enable pin low-to-high transition. this feature allows for an extremely fast startup because the peak detectors never catch a false level created by a startup transient. the peak detectors exhibit a fast-attack/slow- decay response. power-supply connections the max7042 can be powered from a 2.4v to 3.6v supply or a 4.5v to 5.5v supply. the device has an on- chip linear regulator that reduces the 5v supply to 3v needed to operate the chip. to operate the max7042 from a 3v supply, connect dvdd, avdd, and hvin to the 3v supply. when using a 5v supply, connect the supply to hvin only, and con- nect avdd to dvdd. in both cases, bypass dvdd and hvin with a 0.01f capacitor and avdd with a 0.1f capacitor. place all bypass capacitors as close to the respective supply pin as possible. control interface considerations when operating the max7042 with a +4.5v to +5.5v supply voltage, the lnasel, fsel1, fsel2, and en pins can be driven by a microcontroller with either 3v or 5v interface logic levels. when operating the max7042 with a +2.4v to +3.6v supply, the microcon- troller must produce logic levels tha conform to the v ih and v il specifications in the dc electrical characteristics table . data ds- r c ds+ data slicer max7042 figure 3. generating data-slicer threshold data pdmax pdmin rr cc max7042 data slicer peak det peak det figure 4. generating data-slicer threshold using the peak detectors
max7042 layout considerations a properly designed pcb is an essential part of any rf/microwave circuit. on high-frequency inputs and outputs, use controlled-impedance lines and keep them as short as possible to minimize losses and radia- tion. at high frequencies, trace lengths that are on the order of / 10 or longer act as antennas. keeping the traces short also reduces parasitic induc- tance. generally, 1in of a pcb trace adds about 20nh of parasitic inductance. the parasitic inductance can have a dramatic effect on the effective inductance of a passive component. for example, a 0.5in trace con- necting a 100nh inductor adds an extra 10nh of induc- tance or 10%. to reduce the parasitic inductance, use wider traces and a solid ground or power plane below the signal traces. also, use low-inductance connections to ground on all gnd pins, and place decoupling capacitors close to all power-supply connections. 308mhz/315mhz/418mhz/433.92mhz low-power, fsk superheterodyne receiver ______________________________________________________________________________________ 15 31 30 29 28 27 26 910 11 12 1314 15 18 19 20 21 22 23 24 7 6 5 4 c13 c14 c15 c6 x1 c16 rf input c7 l1 rssi xtal2 xtal1 avdd 8 lnain 3.0v lnasel data hvin v dd v dd fsel2 fsel1 en lnasel data fsel2 fsel1 en dvdd dgnd df op+ ds+ ds- pdmax 17 pdmin ifin- agnd 16 ifin+ mixout mixin- exposed p ad mixin+ lnaout lnasrc l3 l2 gnd y1 out in v dd v dd c10 c12 c11 c8 c9 rssi c2 c1 c4 c5 r1 c3 v dd max7042 typical application circuit
max7042 308mhz/315mhz/418mhz/433.92mhz low-power, fsk superheterodyne receiver 16 ______________________________________________________________________________________ chip information process: cmos table 3. component values for typical application circuit component value for 315mhz rf value for 433.92mhz rf description c1 0.01f 0.01f 5% c2 220pf 220pf 5% c3 220pf 220pf 5% c4 470pf 470pf 5% c5 0.047f 0.047f 10% c6 0.1f 0.1f 10% c7 100pf 100pf 10% c8 100pf 100pf 10% c9 1.2pf open 0.1pf c10 220pf 220pf 10% c11 100pf 100pf 10% c12 1500pf 1500pf 10% c13 220pf 220pf 10% c14 100pf 100pf 10% c15 100pf 100pf 10% c16 0.01f 0.01f 10% l1 82nh 39nh 5% or better* l2 30nh 16nh 5% or better* l3 3.9nh short 5% or better* r1 100k ? 100k ? 5% x1 9.50939mhz 13.22563mhz crystal, 4.5pf c load , crystek or hong kong xtals y1 10.7mhz ceramic filter 10.7mhz ceramic filter murata package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 32 tqfn-ep t3255+3 21-0140 90-0001 *wirewound recommended.
max7042 308mhz/315mhz/418mhz/433.92mhz low-power, fsk superheterodyne receiver maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidanc e. 17 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 2 1/12 updated ordering information , absolute maximum ratings , dc and ac electrical characteristics , tocs 5, 6, 7, 11; updated pin configuration , pin description , functional diagram , phase-locked loop section, power-supply connections section, typical application circuit, and table 3. 1C5, 8, 9, 11, 14, 15, 16

▲Up To Search▲

Price & Availability of MAX704212

	To Download MAX704212 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .